1. Field of the Invention
The present invention relates to a phase-locked loop circuit, and particularly to a phase-locked loop circuit capable of providing a lock detection signal after achieving a phase lock state.
2. Description of the Related Art
Phase-locked loop (PLL) circuits are one of the basic building blocks in modern electronic systems. They have enjoyed widespread use in communications, multimedia, and other applications. Frequency synthesizers, FM demodulators, clock recovery circuits, modems, and tone decoders are examples of applications that employ PLL circuits.
The PLL circuit is a negative feedback control system. As shown in FIG. 1, the PLL circuit generally includes a phase-frequency detector (PFD) 100, a charge pump 200, a loop filter 300, a voltage-controlled oscillator (VCO) 400, and a frequency divider 500. The PFD 100 generates an up signal SUP and/or a down signal SDN based on the phase (and/or frequency) difference between a reference signal SIN and a feedback signal SFEED. The charge pump 200 generates an output signal having a level that varies according to the status of the up signal SUP and/or the down signal SDN. The output signal of the charge pump 200 is provided to an input VCOI of the VCO 400 through the loop filter 300, which removes high frequency component of the output signal of the charge pump 200. The VCO 400 generates high frequency signal that varies according to the DC level of the input voltage VCOI. The frequency divider 500 generates the feedback signal SFEED having a low frequency that is based on the high frequency signal output from the VCO 400. The feedback signal SFEED is applied to an input of the PFD 100. When the PLL circuit is in a lock mode, the phase (and/or frequency) of the reference signal SIN and the phase of the feedback signal SFEED are locked. When the PLL circuit is not in the lock mode, the phase (and/or frequency) of the reference signal SIN and the phase of the feedback signal SFEED are not locked.
The output of the VCO 400 may be available only when the PLL circuit is locked. Accordingly, there is a need for a lock detection circuit capable of determining whether the PLL circuit is operating in the lock mode or in the unlock mode. One example of the lock detection circuit is disclosed in Japanese Patent Application Laid-Open Publication No. 2002-344312. However, according to Japanese Patent Application Laid-Open Publication No. 2002-344312, in some situations, lock detection cannot be accurately performed due to noise, and, in those cases, a lock detection signal can be incorrectly generated when the PLL circuit is not in an entirely locked state.
In Korean Patent Application Laid-Open Publication No. 2005-0033896, the applicant of which is the same as that of this invention, a phase-locked loop circuit capable of outputting a lock detection signal when the locking of phase is entirely accomplished using the operating properties of the phase-locked loop circuit is disclosed in an effort to address the aforementioned limitations.